• What is the standardize library packages in VHDL ? and write it down

• What you must to do when you find out that your project not working ?

• What program you should use to program the XS40 chip? And what kind of method you would do to check your board?

• What are the bus design impact?

• What are the disadvantage / advantage of using serial bus ?

• Where would you go after running a simulation to verify that circuit's inputs and outputs were assigned to the correct pins, or if you have any other problems during simulation?

• After generating and checking the Netlist for your logic circuit, how would you make your netlist available in a format that can be used by implementation tools?

• What tool is used to download our project's bitstream file unto the board?

• What is the proper format for pin assignment that maps the I/O signals of the program to the appropriate pins of the board?

• What are the pinouts for the XS40 Board for the 7-segment LED display?

• What are the benefits of renaming specific inputs and outputs?

• Why is it beneficial to have the XS4010XL board connected to the XST-1 extender board?

• Besides the ones that we used in class, what other options are available in the XSTOOLS package and what are they for?

• Which Pins on the XS40 board control the seven-segment display?

• How much additional RAM does the XStend Board add to the XS Board when connected?

• What does VHDL stand for?

• When displaying numbers on the 7-segment LEDs on the XStend 1.3.2 board, what might be affected on the XS40 board due to the sharing of pins on the FPGA?

• What are the labels on the three pushbuttons on the XStend 1.3.2 board? Which one is NOT intended to be a general purpose input, and why?

• When changing the clock speed on the XS Boards using the GXSCLOCK utility, what is the set of valid divisor values for dividing the 100 MHz clock speed?

• The XSV-100 board has a left bank of memory and a right bank of memory. What is the byte address range for each bank of memory?

• Name five (5) features that exist on the XSV-100 board that are not available on the XS40/XStend 1.3.2 boards.

• In order to store a VPGA configuration into the 2 MByte flash memory of the XSV board what file type(s) must be used?
  
  
• On the XSV board how do you program the oscillator for different frequencies? What is the range of frequencies that you can program?
  
  
• Which pins of the XSV parallel port should not be configured as outputs by the CPLD and what is the reason for this?
  
  
• On the XS-40 board why should the DIP switches be left in the open position when not it use.
  
  
• What causes most errors in testing the XS boras using GXSTEST?
  
  
• What specification of USB is present on the XSV board and what is it's maximum bandwidth?
  
  
• In Foundation how do you select a new target device for a project?
  
  
• In Foundation what do we used to create a RAM module internal to the FPGA?
  
  
• How do you add libraries of symbols to a project?
  
  
• In VHDL sequential statements are defined where?
  
  
• Define the following acronyms:
• FPGA
• CPLD
• VHCL
• IDE

• Describe how to load a file onto a FPGA board. Specify which file(s) are used in this procedure.

• State three of the design units in VHDL code. Briefly explain what each unit contains.

• What are the advantages of building circuits from a hierarchy of modules?

• What are the steps taken when creating a logic circuit for a FPGA?

• What is one way that you can assign I/O pin?

• How to do you test the board board?

• How do you download your design to the board?

• When a keyboard(PS/2) is connected to a XS40 board or a XS95 board what two signals are passed through?

• What is one of the advantages building circuits from a hierarchy of modules?

• What 6 general steps are in creating a logic circuit for a CPLD or FPGA in Xilinx?

• Name two advantages of the VHDL description of the FSM.

• What do the two following signals indicate for a PS2 keyboard connection? psData and psClk?

• In VHDL, this indicates when a process is to run?

• Before attempting to program the Flash, you must do what?

• What is Kevin Indrebo's given name?

• How is each bank of SRAM in the XSV-100 organized (in terms of K by bits)?

• What two speeds can the USB port on the XSV-100 be set at?

• How does one set the clock frequency on the XS4010 board?

• What is the purpose of the .ucf file in a Xilinx project?

• What is the gate count on the two boards used in class?

• How do you create a brand new implementation for a project in Project Manager so as to allow for a change, if the implementation has already been allowed to run to completion?

• What are the three modes of Design Entry for the Project Manager software?

• Seeing as how a majority of the time the engineering applications in the 388 lab are not imaged correctly, Where are the GXS Tools physically stored on the machines?

• Approximately how many gates can the XS4010XL board accommodate? And the XSV100 board?

• What does VHDL stand for? And for bonus points what should it really stand for?

• Describe what each of these Foundation 2.1I State machine construction buttons do:
• State button, Transition button, Condition button, Transition Action button, and State Action button.

• What is a trap state in a State diagram?

• What are the IPAD, OPAD, and BUFG components in the schematic editor used for?

• For the XSV-100 board, what does the Divisor field of gxssetclk program do? What is the default clock speed of the oscillator on board?

• What are the 5 design units in VHDL? Explain four of the five.

• How many gates are available with the XS40 boards? With the XS100 boards?

• When I first turn on the XS40 Board, the LED display shows '8' (all segments on). What happened with the board? Is this normal?

• How do you create VHDL code from a schematic?

• What is wrong with the following net assignments?
• NET D0 LOC=P44;
• NET D1 LOC=P45;
• NET D2 LOC=P46;
• NET D3 LOC=P47;
• NET S0 LOC=P25;
• NET S1 LOC=P26;
• NET S2 LOC=P24;
• NET S3 LOC=P20;
• NET S4 LOC=P23;
• NET S5 LOC=P18;
• NET S6 LOC=P19;

• How do you create symbols from VHDL code for higher level schematic diagrams?