Fall 2003 Potential Exam Questions
- Is the PS/clock static high or static low?
- Draw the 7-segment LED display for the XSV board with the LEDs appropriately numbered .
- Describe the steps necessary to take the completed stopwatch project to run a simulation.
- Describe the relationship between the FPGA and the CPLD.
- What are the three styles of modeling circuits with VHDL? Describe them.
- How do you work with the clock on the XSV board?
- What frequency does the XSV board clock run at by default?
- How do you change frequency of the XSV board clock?
- How do you access the XSV board clock from the Virtex FPGA?
- What I/O device are the parallel port pins connected to by default with the dwnldpar.svf file?
- What should the XSV board clock multiplier be set at to achieve a clock rate of 1.333 MHz?
- How many hex digits are stored in each address of the XSV board’s SRAM memory bank?
- What is the purpose of the dwnldpar.svf programming file?
- What is the use of a Language Template and where in Xilinx can you find them?
- What is the name and format of the file used for mapping the input/output signals to pins.
- What is the proper order to load the CPLD and FPGA (.svf and .bit files) including dwnldpar.svf?
- Besides checking the parallel cable and making sure the board is turned on, what is the next best thing to look at if the board fails the test?
- What is the standardize library packages in VHDL ? and write it down
- What tool is used to download our project’s bitstream file unto the board?
- What is the proper format for pin assignment that maps the I/O signals of the program to the appropriate pins of the board?
- What are the pinouts for the XSV Board for the 7-segment LED displays?
- What does VHDL stand for?
- The XSV board has a left bank of memory and a right bank of memory. What is the byte address range for each bank of memory?
- In order to store a FPGA configuration into the 2 MByte flash memory of the XSV board what file type(s) must be used?
- On the XSV board how do you program the oscillator for different frequencies? What is the range of frequencies that you can program?
- Which pins of the XSV parallel port should not be configured as outputs by the CPLD and what is the reason for this?
- What specification of USB is present on the XSV board and what is it’s maximum bandwidth?
- In VHDL sequential statements are defined where?
- Define the following acronyms:
- FPGA
- CPLD
- VHDL
- IDE
- Describe how to load a file onto a FPGA board. Specify which file(s) are used in this procedure.
- State three of the design units in VHDL code. Briefly explain what each unit contains.
- What are the advantages of building circuits from a hierarchy of modules?
- What are the steps taken when creating a logic circuit for a FPGA?
- What is one way that you can assign I/O pins?
- How do you download your design to the board?
- When a keyboard(PS/2) is connected to a XSV board what two signals are passed through?
- What is one of the advantages building circuits from a hierarchy of modules?
- How is each bank of SRAM in the XSV organized (in terms of K by bits)?
- What two speeds can the USB port on the XSV-100 be set at?
- What is the purpose of the .ucf file in a Xilinx project?
- What is the gate count on the XSV board used in class?
- How do you create VHDL code from a schematic?
- How do you create symbols from VHDL code for higher level schematic diagrams?